module ram2PortEnqueueCrossBar (
    input wire clk,
    input wire rst,
    input wire [15:0] enqueue_en_in,
    input wire [5:0] enqueue_priority_in [0:15],
    input wire [9:0] enqueue_value_in [0:15],
    input wire [15:0] enqueue_port_in [0:15],
    input wire [15:0] enqueue_sucess,
    input wire [15:0] enqueue_ack,
    output reg [15:0] enqueue_en_out,
    output reg [5:0] enqueue_priority_out [0:15],
    output reg [15:0] enqueue_value_out [0:15]
);  
    //出队信号
    wire [15:0] enqueue_en_ram1;
    wire [15:0] enqueue_en_ram2;
    wire [15:0] enqueue_en_ram3;
    wire [15:0] enqueue_en_ram4;
    wire [15:0] enqueue_en_ram5;
    wire [15:0] enqueue_en_ram6;
    wire [15:0] enqueue_en_ram7;
    wire [15:0] enqueue_en_ram8;
    wire [15:0] enqueue_en_ram9;
    wire [15:0] enqueue_en_ram10;
    wire [15:0] enqueue_en_ram11;
    wire [15:0] enqueue_en_ram12;
    wire [15:0] enqueue_en_ram13;
    wire [15:0] enqueue_en_ram14;
    wire [15:0] enqueue_en_ram15;
    wire [15:0] enqueue_en_ram16;
    wire [5:0] enqueue_priority_ram1 [0:15];
    wire [5:0] enqueue_priority_ram2 [0:15];
    wire [5:0] enqueue_priority_ram3 [0:15];
    wire [5:0] enqueue_priority_ram4 [0:15];
    wire [5:0] enqueue_priority_ram5 [0:15];
    wire [5:0] enqueue_priority_ram6 [0:15];
    wire [5:0] enqueue_priority_ram7 [0:15];
    wire [5:0] enqueue_priority_ram8 [0:15];
    wire [5:0] enqueue_priority_ram9 [0:15];
    wire [5:0] enqueue_priority_ram10 [0:15];
    wire [5:0] enqueue_priority_ram11 [0:15];
    wire [5:0] enqueue_priority_ram12 [0:15];
    wire [5:0] enqueue_priority_ram13 [0:15];
    wire [5:0] enqueue_priority_ram14 [0:15];
    wire [5:0] enqueue_priority_ram15 [0:15];
    wire [5:0] enqueue_priority_ram16 [0:15];
    wire [9:0] enqueue_value_ram1 [0:15];
    wire [9:0] enqueue_value_ram2 [0:15];
    wire [9:0] enqueue_value_ram3 [0:15];
    wire [9:0] enqueue_value_ram4 [0:15];
    wire [9:0] enqueue_value_ram5 [0:15];
    wire [9:0] enqueue_value_ram6 [0:15];
    wire [9:0] enqueue_value_ram7 [0:15];
    wire [9:0] enqueue_value_ram8 [0:15];
    wire [9:0] enqueue_value_ram9 [0:15];
    wire [9:0] enqueue_value_ram10 [0:15];
    wire [9:0] enqueue_value_ram11 [0:15];
    wire [9:0] enqueue_value_ram12 [0:15];
    wire [9:0] enqueue_value_ram13 [0:15];
    wire [9:0] enqueue_value_ram14 [0:15];
    wire [9:0] enqueue_value_ram15 [0:15];
    wire [9:0] enqueue_value_ram16 [0:15];
    wire [15:0] enqueue_en_temp;
    wire [5:0] enqueue_priority_temp [0:15];
    wire [15:0] enqueue_value_temp [0:15];
    reg [5:0] history_ram_no [0:15];

    integer i;
    reg [1:0] work_state [0:15];
    reg [3:0] counter;

    always @(posedge clk) begin
        if (rst) begin
            for (i=0; i<16; i=i+1) begin
                work_state[i] <= 2'b00;
                history_ram_no[i] <= 0;
            end
        end
        else begin
            for (i=0; i<16; i=i+1) begin
                if (enqueue_en_temp[i]==1 && work_state[i]==2'b00) begin
                    enqueue_en_out[i] <= 1'b1;
                    enqueue_priority_out[i] <= enqueue_priority_temp[i];
                    enqueue_value_out[i] <= enqueue_value_temp[i];
                    history_ram_no[i] <= enqueue_value_temp[i][15:10] - 16;
                    work_state[i] <= 2'b01;
                end

                if (enqueue_ack[history_ram_no[i]] && enqueue_sucess[i]==1 && work_state[i]==2'b01) begin
                    enqueue_en_out[i] <= 0;
                    enqueue_priority_out[i] <= 0;
                    work_state[i] <= 2'b10;
                    counter <= 0;
                end

                if (work_state[i]==2'b10) begin
                    if (counter == 3) begin
                        work_state[i] <= 2'b00;
                    end
                    counter <= counter + 1;
                end
            end
        end
    end


    enqueueRamDeMuxer16 ram1DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[0]), .enqueue_priority_in(enqueue_priority_in[0]), .enqueue_value_in(enqueue_value_in[0]), .enqueue_port_in(enqueue_port_in[0]), 
                                .enqueue_en_out(enqueue_en_ram1), .enqueue_priority_out(enqueue_priority_ram1), .enqueue_value_out(enqueue_value_ram1));

    enqueueRamDeMuxer16 ram2DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[1]), .enqueue_priority_in(enqueue_priority_in[1]), .enqueue_value_in(enqueue_value_in[1]), .enqueue_port_in(enqueue_port_in[1]), 
                                .enqueue_en_out(enqueue_en_ram2), .enqueue_priority_out(enqueue_priority_ram2), .enqueue_value_out(enqueue_value_ram2));

    enqueueRamDeMuxer16 ram3DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[2]), .enqueue_priority_in(enqueue_priority_in[2]), .enqueue_value_in(enqueue_value_in[2]), .enqueue_port_in(enqueue_port_in[2]), 
                                .enqueue_en_out(enqueue_en_ram3), .enqueue_priority_out(enqueue_priority_ram3), .enqueue_value_out(enqueue_value_ram3));

    enqueueRamDeMuxer16 ram4DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[3]), .enqueue_priority_in(enqueue_priority_in[3]), .enqueue_value_in(enqueue_value_in[3]), .enqueue_port_in(enqueue_port_in[3]), 
                                .enqueue_en_out(enqueue_en_ram4), .enqueue_priority_out(enqueue_priority_ram4), .enqueue_value_out(enqueue_value_ram4));

    enqueueRamDeMuxer16 ram5DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[4]), .enqueue_priority_in(enqueue_priority_in[4]), .enqueue_value_in(enqueue_value_in[4]), .enqueue_port_in(enqueue_port_in[4]), 
                                .enqueue_en_out(enqueue_en_ram5), .enqueue_priority_out(enqueue_priority_ram5), .enqueue_value_out(enqueue_value_ram5));

    enqueueRamDeMuxer16 ram6DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[5]), .enqueue_priority_in(enqueue_priority_in[5]), .enqueue_value_in(enqueue_value_in[5]), .enqueue_port_in(enqueue_port_in[5]), 
                                .enqueue_en_out(enqueue_en_ram6), .enqueue_priority_out(enqueue_priority_ram6), .enqueue_value_out(enqueue_value_ram6));

    enqueueRamDeMuxer16 ram7DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[6]), .enqueue_priority_in(enqueue_priority_in[6]), .enqueue_value_in(enqueue_value_in[6]), .enqueue_port_in(enqueue_port_in[6]), 
                                .enqueue_en_out(enqueue_en_ram7), .enqueue_priority_out(enqueue_priority_ram7), .enqueue_value_out(enqueue_value_ram7));

    enqueueRamDeMuxer16 ram8DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[7]), .enqueue_priority_in(enqueue_priority_in[7]), .enqueue_value_in(enqueue_value_in[7]), .enqueue_port_in(enqueue_port_in[7]), 
                                .enqueue_en_out(enqueue_en_ram8), .enqueue_priority_out(enqueue_priority_ram8), .enqueue_value_out(enqueue_value_ram8));

    enqueueRamDeMuxer16 ram9DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[8]), .enqueue_priority_in(enqueue_priority_in[8]), .enqueue_value_in(enqueue_value_in[8]), .enqueue_port_in(enqueue_port_in[8]), 
                                .enqueue_en_out(enqueue_en_ram9), .enqueue_priority_out(enqueue_priority_ram9), .enqueue_value_out(enqueue_value_ram9));

    enqueueRamDeMuxer16 ram10DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[9]), .enqueue_priority_in(enqueue_priority_in[9]), .enqueue_value_in(enqueue_value_in[9]), .enqueue_port_in(enqueue_port_in[9]), 
                                .enqueue_en_out(enqueue_en_ram10), .enqueue_priority_out(enqueue_priority_ram10), .enqueue_value_out(enqueue_value_ram10));

    enqueueRamDeMuxer16 ram11DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[10]), .enqueue_priority_in(enqueue_priority_in[10]), .enqueue_value_in(enqueue_value_in[10]), .enqueue_port_in(enqueue_port_in[10]), 
                                .enqueue_en_out(enqueue_en_ram11), .enqueue_priority_out(enqueue_priority_ram11), .enqueue_value_out(enqueue_value_ram11));

    enqueueRamDeMuxer16 ram12DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[11]), .enqueue_priority_in(enqueue_priority_in[11]), .enqueue_value_in(enqueue_value_in[11]), .enqueue_port_in(enqueue_port_in[11]), 
                                .enqueue_en_out(enqueue_en_ram12), .enqueue_priority_out(enqueue_priority_ram12), .enqueue_value_out(enqueue_value_ram12));

    enqueueRamDeMuxer16 ram13DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[12]), .enqueue_priority_in(enqueue_priority_in[12]), .enqueue_value_in(enqueue_value_in[12]), .enqueue_port_in(enqueue_port_in[12]), 
                                .enqueue_en_out(enqueue_en_ram13), .enqueue_priority_out(enqueue_priority_ram13), .enqueue_value_out(enqueue_value_ram13));

    enqueueRamDeMuxer16 ram14DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[13]), .enqueue_priority_in(enqueue_priority_in[13]), .enqueue_value_in(enqueue_value_in[13]), .enqueue_port_in(enqueue_port_in[13]), 
                                .enqueue_en_out(enqueue_en_ram14), .enqueue_priority_out(enqueue_priority_ram14), .enqueue_value_out(enqueue_value_ram14));

    enqueueRamDeMuxer16 ram15DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[14]), .enqueue_priority_in(enqueue_priority_in[14]), .enqueue_value_in(enqueue_value_in[14]), .enqueue_port_in(enqueue_port_in[14]), 
                                .enqueue_en_out(enqueue_en_ram15), .enqueue_priority_out(enqueue_priority_ram15), .enqueue_value_out(enqueue_value_ram15));

    enqueueRamDeMuxer16 ram16DeMux(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess),
                                .enqueue_en_in(enqueue_en_in[15]), .enqueue_priority_in(enqueue_priority_in[15]), .enqueue_value_in(enqueue_value_in[15]), .enqueue_port_in(enqueue_port_in[15]), 
                                .enqueue_en_out(enqueue_en_ram16), .enqueue_priority_out(enqueue_priority_ram16), .enqueue_value_out(enqueue_value_ram16));



    genvar emIndex;
    generate
        for (emIndex=0; emIndex<16; emIndex=emIndex+1) begin : enqueueMuxer
            enqueueMuxer32 muxerForEnqueue(.clk(clk), .rst(rst), .enqueue_sucess(enqueue_sucess[emIndex]),
                                        .queue_en_1(enqueue_en_ram1[emIndex]), .queue_en_2(enqueue_en_ram2[emIndex]), .queue_en_3(enqueue_en_ram3[emIndex]), .queue_en_4(enqueue_en_ram4[emIndex]), .queue_en_5(enqueue_en_ram5[emIndex]), .queue_en_6(enqueue_en_ram6[emIndex]), .queue_en_7(enqueue_en_ram7[emIndex]), .queue_en_8(enqueue_en_ram8[emIndex]), .queue_en_9(enqueue_en_ram9[emIndex]), 
                                        .queue_en_10(enqueue_en_ram10[emIndex]), .queue_en_11(enqueue_en_ram11[emIndex]), .queue_en_12(enqueue_en_ram12[emIndex]), .queue_en_13(enqueue_en_ram13[emIndex]), .queue_en_14(enqueue_en_ram14[emIndex]), .queue_en_15(enqueue_en_ram15[emIndex]), .queue_en_16(enqueue_en_ram16[emIndex]),
                                        .enqueue_priority_1(enqueue_priority_ram1[emIndex]), .enqueue_priority_2(enqueue_priority_ram2[emIndex]), .enqueue_priority_3(enqueue_priority_ram3[emIndex]), .enqueue_priority_4(enqueue_priority_ram4[emIndex]), .enqueue_priority_5(enqueue_priority_ram5[emIndex]), .enqueue_priority_6(enqueue_priority_ram6[emIndex]), .enqueue_priority_7(enqueue_priority_ram7[emIndex]), .enqueue_priority_8(enqueue_priority_ram8[emIndex]), .enqueue_priority_9(enqueue_priority_ram9[emIndex]),
                                        .enqueue_priority_10(enqueue_priority_ram10[emIndex]), .enqueue_priority_11(enqueue_priority_ram11[emIndex]), .enqueue_priority_12(enqueue_priority_ram12[emIndex]), .enqueue_priority_13(enqueue_priority_ram13[emIndex]), .enqueue_priority_14(enqueue_priority_ram14[emIndex]), .enqueue_priority_15(enqueue_priority_ram15[emIndex]), .enqueue_priority_16(enqueue_priority_ram16[emIndex]), 
                                        .enqueue_index_1(enqueue_value_ram1[emIndex]), .enqueue_index_2(enqueue_value_ram2[emIndex]), .enqueue_index_3(enqueue_value_ram3[emIndex]), .enqueue_index_4(enqueue_value_ram4[emIndex]), .enqueue_index_5(enqueue_value_ram5[emIndex]), .enqueue_index_6(enqueue_value_ram6[emIndex]), .enqueue_index_7(enqueue_value_ram7[emIndex]), .enqueue_index_8(enqueue_value_ram8[emIndex]), .enqueue_index_9(enqueue_value_ram9[emIndex]),
                                        .enqueue_index_10(enqueue_value_ram10[emIndex]), .enqueue_index_11(enqueue_value_ram11[emIndex]), .enqueue_index_12(enqueue_value_ram12[emIndex]), .enqueue_index_13(enqueue_value_ram13[emIndex]), .enqueue_index_14(enqueue_value_ram14[emIndex]), .enqueue_index_15(enqueue_value_ram15[emIndex]), .enqueue_index_16(enqueue_value_ram16[emIndex]),
                                        .enqueue_out(enqueue_en_temp[emIndex]), .enqueue_priority_out(enqueue_priority_temp[emIndex]), .enqueue_value_out(enqueue_value_temp[emIndex]));
        end
    endgenerate

endmodule